Performance issus with logic simulation

General FreeBASIC programming questions.
IchMagBier
Posts: 52
Joined: Jan 13, 2018 8:47
Location: Germany
Contact:

Performance issus with logic simulation

Postby IchMagBier » Nov 27, 2018 5:21

Hello!

So after coding my Gameboy emulator, I have decided to go more lowlevel and make a CPU simulator (like https://simulator.io/for example).
Basically I can set my own logic gates and wire them on a big board. So I got AND-gates, OR, XOR, Buttons ... etc. Looks like this:

Code: Select all

type t_wire
   as ubyte value
end type

type t_gate
   as ubyte typ
   as t_wire ptr in1(7),in2(7),out(7)
   as t_gate ptr next
end type

sub update()
   do
      select case as const gate->typ
         case C_AND
            for i = 0 to 7
               gate->out(i)->value = gate->in1(i)->value and gate->in2(i)->value
            next
      end select
      gate = gate->next
   loop until gate = 0
end sub

However, this is really slow. Every wire is one single bit, so it should be possible to do all of them with one single operation, instead of having a for-loop. I also wouldn't need arrays for every input/output:

Code: Select all

type t_gate
   as ubyte typ
   as t_wire ptr in1,in2,out
   as t_gate ptr next
end type

sub update()
   do
      select case as const gate->typ
         case C_AND
            gate->out->value = gate->in1->value and gate->in2->value
      end select
      gate = gate->next
   loop until gate = 0
end sub

But what if some inputs come from another wire? I can't figure out how to make it more performant without losing functionality.
I drew a pretty picture to show you what I mean:
Image
Top shows the fast and ideal solution, where in1, in2 and out are one wire. Bottom shows the problem, where in1 and out are more than one wire. The 8 AND-gates are a single one in the code.

SOLVED
I just let the program generate and compile some ASM-code, which represents the logic-gates. This is fast enough.
D.J.Peters
Posts: 8117
Joined: May 28, 2005 3:28
Contact:

Re: Performance issus with logic simulation

Postby D.J.Peters » Nov 27, 2018 9:25

I created a logic simulator at late 80th's in Java
the biggest problem was to simulate closed loops with feedback.

For example the user connect the output of an NOR to the input of the same NOR.

Do you solved the kind of feedback loop problem also ?

Joshy
IchMagBier
Posts: 52
Joined: Jan 13, 2018 8:47
Location: Germany
Contact:

Re: Performance issus with logic simulation

Postby IchMagBier » Nov 28, 2018 4:37

Well, not sure what I should expect:
Image
Seems to work like in other logic simulators. Same results in BOOLR and simulator.io.

Return to “General”

Who is online

Users browsing this forum: Baidu [Spider] and 6 guests